Clock recovery circuits have been used for years using a ringing tank circuit wherein the occurence of a change in signal amplitude from a logic "1" to a logic "0" or vice versa has imparted energy into a inductive capacitive circuit and produced a ringing effect at the output of this circuit. These analog ringing tank circuits are notorious for needing adjustment, for changing characteristics with age of components, etc. Further, the ringing tank circuit has an output signal, which by definition, slowly decays over a period of time and if only a single logic value is received over a long period of time, energy is not added to the circuit to replace that dissipated. Thus, the oscillator circuit which is receiving its timing information from the ringing tank circuit, quickly falls out of synchronization with the incoming data and, upon the next receipt of a logic "1", the circuit timing is often so far off that complete circuit signal resynchronization has to take place.
The present invention on the other hand uses digital circuitry to divide or count a very stable and high speed clock to produce a lower speed "recovered clock" which is as stable as the initial clock. The phase of this recovered clock is adjusted by adjusting a dividing or counting circuit whenever a "valid" logic level excursion is detected. By eliminating action in response to logic level excursions of less than a predetermined time and by preventing phase adjustment during an entire period equivalent to a given data signal, the circuit can substantially eliminate any false phase adjustments due to signal transients, etc.
It is thus an object of the present invention to provide an improved clock recovery circuit.